ISL6432CB-T【PDF 6/12 页】IC REG QD BCK/LINEAR 16-SOIC

6

three-cycle wait, the fourth soft-start initiates a ramp-up

attempt of the failed output, at time T2, bringing the output in

regulation at time T4.

To exemplify an UV event on one of the linears, at time T1,

the clock regulator (V

OUT2

) is also subjected to an

overcurrent event, resulting in an UV condition. Similarly,

after three soft-start periods, the fourth cycle initiates a

ramp-up of this linear output at time T3. One soft-start period

after T3, the linear output is within regulation limits. UV

glitches less than 1祍 (typically) in duration are ignored.

As overcurrent protection is performed on the synchronous

switcher regulator on a cycle-by-cycle basis, OC monitoring

is active as long as the regulator is operational. Since the

overcurrent protection on the linear regulators is performed

through undervoltage monitoring at the feedback pins (FB2,

FB3, and FB4), this feature is activated approximately 25%

into the soft-start interval (see Figure 1).

A resistor (R

OCSET

) programs the overcurrent trip level for

the PWM converter. As shown in Figure 2, the internal

40礎 current sink (I

OCSET

) develops a voltage across

R

OCSET

(V

SET

) that is referenced to V

IN

. The DRIVE

signal enables the overcurrent comparator (OCC). When

the voltage across the upper MOSFET (V

DS(ON)

) exceeds

V

SET

, the overcurrent comparator trips to set the

overcurrent latch. Both V

SET

and V

DS(ON)

are referenced

to V

IN

and a small capacitor across R

OCSET

helps V

OCSET

track the variations of V

IN

due to MOSFET switching. The

overcurrent function will trip at a peak inductor current

(I

PEAK)

determined by:

The OC trip point varies with MOSFETs r

DS(ON)

temperature variations. To avoid overcurrent tripping in the

normal operating load range, determine the R

OCSET

resistor from the equation above with:

1. The maximum r

DS(ON)

at the highest junction temperature.

2. The minimum I

OCSET

from the specification table.

3. Determine I

PEAK

for I

PEAK

> I

OUT(MAX)

+ (I)/2, where

I is the output inductor ripple current.

For an equation for the ripple current see the section under

component guidelines titled Output Inductor Selection.

Output Voltage Selection

The output voltage of the PWM converter can be resistor-

programmed to any level between V

IN

and 0.8V. However,

since the value of R

S1

is affecting the values of the rest of

the compensation components, it is advisable its value is

kept between 2k& and 5k&.

All linear regulators output voltages are set by means of

external resistor dividers as shown in Figure 3. The two

resistors used to set the voltage on each of the three linear

regulators have to meet the following criteria: their value

while in a parallel connection has to be less than 5k&, or

otherwise said, the following relationship has to be met:

FIGURE 1. OVERCURRENT/UNDERVOLTAGE PROTECTION

RESPONSE

0V

TIME

(0.5V/DIV.)

V

OUT3

(1.8V)

V

OUT2

(2.5V)

T1

T2

T3

T0

V

OUT4

(1.5V)

V

OUT1

(2.5V)

UV MONITORING

INACTIVE

SOFT-START

FUNCTION

ACTIVE

T4

I

PEAK

=

I

OCSET

R

OCSET

?/DIV>

r

DS ON

( )

--------------------------------------------------- -

UGATE

OCSET

PHASE

OCC

+

-

GATE

CONTROL

VCC

OC

40?/SPAN>A

V

DS(ON)

i

D

V

SET

R

OCSET

V

IN

= +5V

OVERCURRENT TRIP:

I

OCSET

+

FIGURE 2. OVERCURRENT DETECTION

PWM

DRIVE

i

D

r

DS ON

( )

?/DIV>

??/DIV>

?/DIV>

I

OCSET

R

OCSET

?/DIV>

??/DIV>

?/DIV>

>

V

DS

V

SET

>

V

PHASE

V

IN

V

DS

=

V

OCSET

V

IN

V

SET

=

DRIVE3

FB3

FB4

C

OUT4

C

OUT3

Q4

ISL6432

V

OUT3

V

OUT4

Q5

+3.3V

IN

DRIVE4

R

S3

R

P3

R

S4

R

P4

V

OUT

0.8 1

R

S

R

P

------- -

+

?/DIV>

=

FIGURE 3. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF

THE FOUR REGULATORS (OUTPUTS 3 AND 4

PICTURED)

+

R

S

R

P

?/DIV>

R

S

R

P

+

--------------------- - 5k&

<

ISL6432

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